The present invention is related to an inrush current suppression circuit, and more particularly, to an inrush current suppression circuit of a power input module in a communication power system.
An inrush current occurs frequently at the moment when the power starts up. At such a moment, an unpredictable and undesirable transient current happens. This may easily induce a noise, and even the power elements or the load could be damaged.
FIG. 1 shows an inrush current suppression circuit applied to a DC (direct current) power according to the prior art. A resistor R, a controlled switch SW, and an energy-storing capacitor C are electrically connected between an input DC voltage U and a system which includes a load and a parallel system capacitor Cs so as to limit the inrush current. At the beginning when the power of a power supply starts, the resistor R initially limits the current. Because the energy-storing capacitor does not begin to charge at this moment, the whole current is very large and thus may damage the components of the power supply. Subsequently, the capacitor is charged, and then the current is lowered. However, the value of current is still large, this making the resistor to produce heat continually. Finally, the controlled switch SW, such as a relay, is conducted to bypass the resistor R so as to avoid lowering the entire efficiency which is caused by the heat. One of the disadvantages of the prior art is that the relay, which endures to be conducted, is easily damaged. Moreover, at the moment when the relay is conducted, another type of inrush current is induced, this may damage the whole power supply.
It is an objective of the present invention to provide an inrush current suppression circuit for safely and stably suppressing the inrush current by means of soft turned-on.
It is another objective of the present invention to provide an inrush current suppression circuit where the energy consumption between the input voltage and load is low, so that it can be applied to those equipments, such as a network system, which consume low power.
According to a preferred embodiment of the present invention, the inrush current suppression circuit is installed between a DC voltage and a load with a parallel system capacitor. The inrush current suppression circuit includes a first current limiting circuit which includes a first resistor, a first controlled switch, and a second controlled switch in which the first controlled switch and the first resistor are electrically connected in series, and the second controlled switch is electrically connected in parallel to the first controlled switch and the first resistor. The inrush current suppression circuit further includes a second current limiting circuit which further includes a second resistor; a third controlled switch; and a energy-storing capacitor in which the second resistor and the capacitor are electrically connected in series, the second resistor is electrically connected in parallel to the third controlled switch. The second current limiting circuit is electrically connected in parallel to a system capacitor, and the first current limiting circuit is electrically connected with the DC voltage and the second current limiting circuit. When the DC voltage is detected, the first controlled switch is conducted. When the voltage of two ends of the load reaches a first threshold value, the second controlled switch is conducted so as to bypass the first resistor. When a voltage of the energy-storing capacitor reaches a second threshold value, the third controlled switch is conducted so as to bypass the second resistor.
Preferably, the load is a DCxe2x80x94DC converter.
Preferably, the first controlled switch is selected from a group consisting of a relay, a bipolar transistor, and a MOSFET (metal-oxide-semiconductor field-effect transistor).
Preferably, the second controlled switch is a MOSFET.
Preferably, the third controlled switch is a MOSFET.
Preferably, the first threshold value is from 30% to 80% of the DC voltage.
Preferably, the first threshold value is from 50% to 70% of the DC voltage.
Preferably, the second threshold value is from 70% to 100% of the DC voltage.
Preferably, the second threshold value is from 80% to 100% of the DC voltage.
Preferably, the second controlled switch is soft turned-on.
Preferably, the third controlled switch is soft turned-on.
According to another preferred embodiment of the present invention, the inrush current suppression circuit is installed between a DC voltage and a load with a parallel system capacitor. The inrush current suppression circuit includes a first current limiting circuit which further includes a first resistor, a first controlled switch, and a second controlled switch in which the first controlled switch and the first resistor are electrically connected in series, and the second controlled switch is electrically connected in parallel to the first controlled switch and the first resistor. The inrush current suppression circuit further includes a second current limiting circuit which further includes a second resistor; a third controlled switch; and a energy-storing capacitor in which the second resistor and the capacitor are electrically connected in series, the second resistor is electrically connected in parallel to the third controlled switch. The second current limiting circuit is electrically connected in parallel to a system capacitor, and the first current limiting circuit is electrically connected with the DC voltage and the second current limiting circuit. When the DC voltage is detected, the first controlled switch is conducted. When the voltage of two ends of the load reaches a first threshold value, the second controlled switch is soft turned-on so as to bypass the first resistor. When a voltage of the energy-storing capacitor reaches a second threshold value, the third controlled switch is soft turned-on so as to bypass the second resistor.
Now the foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the drawings, wherein: